Method of utilizing a plurality of voltage pulses to program non-volatile memory elements and related embedded memories

ABSTRACT

A method and related embedded memories are disclosed for utilizing a plurality of voltage pulses to program non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. To write the antifuse element, a plurality of voltage pulses are used to provide a rapid series of charge flows through the antifuse element. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention relates to non-volatile memories, and more particularly, to embedded memories for combination with other integrated circuitry.

BACKGROUND

[0002] Data in digital systems, such as computers, cell phones, automotive and industrial controllers, etc. is generally stored in volatile and non-volatile memories. Volatile storage refers to data that is only valid while power is maintained, while non-volatile memory will maintain data even without power. There are existing non-volatile memory solutions such as EPROM, EEPROM, and Flash memories as well as ROM. ROM is fabricated with a fixed data pattern, which can never be altered. ROM is useful, therefore, when the information to be stored is known at the time of manufacture. Many applications, however, need to store information during operation or after installation. Those that only need a small amount of operational storage, such as calibration data for analog settings and configuration data for digital systems that have built in flexibility, can utilize memory that can be written with the needed parameters determined during installation or during a calibration process and that can then be accessed to provide the stored parameters during future operations.

[0003] For this reason, it is often desirable to include with other integrated circuitry memory that can be written with data so that a single integrated circuit can provide both operational functions and the data storage functions. Usually, memory combined in such a integrated circuit is referred to as embedded memory, because the memory is added into the digital design. One difficulty, however, is that the processes utilized to manufacture memory circuitry may not be compatible with the processes used to manufacture the logic, control or other integrated circuitry.

[0004] EPROM, EEPROM and Flash memory are all types of memory that store information by writing to the device during operation and would, therefore, be desirable for embedded applications. However, these devices generally use a storage transistor that has a floating gate, and charge is added or subtracted from this floating gate to store the binary states. Problematically, these floating gate technologies are normally fabricated on processes specifically tailored to the floating gate implementations. And the manufacturing process to make these floating gate devices is more complicated and more costly than standard CMOS technology. In addition, the floating gate processes will generally produce a lower performance logic (or digital) device because the additional processing required for the floating gate devices will often cause changes (generally degradation) in the performance of the basic CMOS transistors. Thus, high performance digital devices and floating gate memories are typically not compatible within the same integrated circuit. For this reason, it is difficult to maintain a high performance digital system with Flash memory added to a single integrated circuit.

[0005] Non-volatile memory solutions have been fabricated as stand alone components for many years, and these solutions have utilized various memory cell structures. Early memories were made of arrays of fuses which could be selectively blown by high current. A fuse device typically refers to a device that starts as a low resistance element (i.e., short circuit) and is made to be a high resistance element by some action, such as high current. This fuse method was often used in bipolar technology because high currents are needed for writing or to blow the fuse and because bipolar transistors can deliver large currents.

[0006] Antifuse devices were also developed for non-volatile data storage. An antifuse structure refers to a device that starts as a high value resistance and is altered (i.e., in writing) to have a much lower value of resistance. Since these devices work in reverse of fuse elements, they are called antifuse elements. Typically, antifuse elements require some particular manufacturing characteristics to permit the formation of devices that can be altered as antifuse devices. Problems with antifuse implementations have included reliability issues associated with large variations in the final resistance of different antifuse elements that had been written. Thus, the use of antifuse elements has been limited. Other antifuse devices have been developed that use special features of a manufacturing process to make an antifuse element, such as using oxide-nitride-oxide (ONO) as a dielectric in the antifuse elements. This ONO structure has been used in DRAM manufacturing processes, but this ONO structure has not been generally available in standard CMOS processes for other types of CMOS integrated circuits.

SUMMARY OF THE INVENTION

[0007] The present invention provides a method of utilizing a plurality of voltage pulses to program non-volatile memory elements and related embedded memories. The non-volatile memory cells and associated programming methods of the present invention allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture other CMOS circuitry. The non-volatile memory cell structure and related programming methods and embedded memories of the present invention, therefore, provide a desirable solution for embedded memory architectures.

[0008] In one embodiment, the present invention is a method for utilizing a plurality of voltage pulses to program a non-volatile memory cell integratable with other CMOS circuitry. The method includes providing an antifuse element having a programming node such that the antifuse element is configured to have reduced resistivity after the programming node is subjected to a plurality of voltage pulses and such that the change in resistivity representing a change in logic state. In addition, the antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the plurality of voltage pulses. The method further includes coupling a capacitor element to the programming node of the antifuse element where the capacitor element is configured to provide the plurality of voltage pulses to the programming node to write the antifuse element.

[0009] In another embodiment, the present invention is an embedded non-volatile memory integrated with other CMOS circuitry that uses a plurality of voltage pulses to write non-volatile memory cells. The embedded memory includes a plurality of non-volatile memory cells and write circuitry coupled to the cells. Each cell includes an antifuse element having a programming node, a capacitor element coupled to the antifuse element, and an access element coupled to the programming node. The antifuse element is configured to have reduced resistivity after the programming node is subjected to a plurality of voltage pulses where the change in resistivity representing a change in logic state. In addition, the antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the plurality of voltage pulses. The capacitor element is configured to provide the plurality of voltage pulses to the programming node. And the access element is configured to allow determination of the logic state for the antifuse element. The write circuitry is coupled to the capacitor elements of the plurality of non-volatile memory cells, and the write circuitry is configured to provide the plurality of voltage pulses to the capacitor elements for writing the antifuse elements.

DESCRIPTION OF THE DRAWINGS

[0010] It is noted that the appended drawings illustrate only exemplary embodiments of the invention and are, therefore, not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0011]FIG. 1A is a block diagram for integrated circuit including embedded non-volatile memory according to the present invention.

[0012]FIG. 1B is a block diagram for an embedded non-volatile memory block including a dual bank cell array.

[0013]FIG. 2 is a circuit diagram for a non-volatile memory element according to the present invention including an antifuse element M1, a writing capacitor C1 and an access transistor M2.

[0014]FIG. 3A is a cross-section diagram for the non-volatile antifuse element M1.

[0015]FIG. 3B is a cross-section diagram for an alternative embodiment for the non-volatile antifuse element M1 in which a voltage gradient is utilized.

[0016] FIGS. 4A-4B are a cross-section perspective diagrams for further embodiments for the non-volatile antifuse element M1 in which additional voltage gradients are utilized.

[0017]FIG. 5A is a graphical diagram for writing to the non-volatile antifuse element M1 including voltage pulses at NODE 4 and corresponding current flows from NODE 4 into the gate of the antifuse element M1.

[0018]FIG. 5B is an example block diagram depicting non-volatile memory cells according to the present invention coupled to other control circuitry.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention provides non-volatile memory cell and associated programming methods that allow for the integration of non-volatile memory with other CMOS circuitry utilizing the standard CMOS processing used to manufacture other CMOS circuitry. Thus, the non-volatile memory cell structure and programming methods of the present invention provide a desirable solution for embedded memory architectures.

[0020]FIG. 1A is a block diagram for integrated circuit 108 including embedded non-volatile memory 100 according to the present invention. As discussed in more detail below, the non-volatile memory cell architecture of the present invention lends itself to being manufactured using standard CMOS processing. Thus, rather than requiring additional processing steps or post processing combination, the embedded non-volatile memory of the present invention can be fabricated at the same time the other CMOS circuitry is being fabricated. As such, integrated circuit 108 can include a wide variety of other circuitry as represented by input/output (I/O) circuitry 104 and processor, control and/or logic circuitry 102. It is noted, therefore, that the actual circuitry fabricated with embedded non-volatile memory 100 could vary depending upon the operational functionality desired.

[0021]FIG. 1B is a block diagram for an embedded non-volatile memory block 100. In the embodiment depicted, the embedded non-volatile memory block 100 has been broken in to a dual bank array so that non-volatile cell array 120A and non-volatile memory cell array 120B make up the available memory for the memory block 100. Also shown is control and data path circuitry 122 that provides control and communication functions for the memory array block 100. It is noted that the actual circuitry implemented for the memory block 100 could vary depending upon the operational functionality desired.

[0022]FIG. 2 is a circuit diagram for a non-volatile memory element 200 according to the present invention including an antifuse element (M1) 206, a writing capacitor (C1) 204 and an access transistor (M2) 202. In operation, NODE 1 is connected to the gate of the access transistor M2 to control its operation. NODE 2 is coupled through the access transistor M2 to the internal NODE 4. The capacitor C1 is connected between NODE 3 and NODE 4. NODE 4 is connected to the gate of antifuse element transistor M1. NODE5 is connected to the source of the transistor M1, and NODE 6 is connected to the drain of transistor M1. As shown, the transistors are NMOS devices. It is noted that PMOS transistors or other device types could be utilized, if desired, for the access device. The capacitor C1 may be a MOS transistor connected such that the gate provides one terminal of the capacitor C1 and such that the source and drain are connected together to provide the other terminal of the capacitor C1. The capacitor C1 could also be formed through other techniques, as desired, such as being formed by using by two conductive layers of metal or polysilicon and a dielectric layer to form a capacitor structure.

[0023] The non-volatile memory element 200 advantageously utilizes an antifuse element 206 that can be fabricated in standard CMOS processes without requiring special processing. This antifuse element 206 can be formed, for example, by using a standard gate oxide dielectric as an insulator. This insulator can then be made to become conductive by electrical means. For example, insulating layers, such as silicon dioxide (SiO₂), can have a voltage applied across them, and the insulator will not permit current to flow. If a sufficiently high field is applied, however, the oxide will break down and cause a fast discharge of the voltage across the oxide. This rapid discharge usually results in a change in the oxide or damage to the oxide that eliminates its insulating characteristic, so that the oxide will now conduct electrical current. This change in resistivity or conductive state can be used to represent the logic state of the antifuse element.

[0024] To cause the dielectric to become conductive, a voltage of sufficient magnitude must typically be applied across the dielectric. Oxides will generally become conductive with exposure to high voltages where stress is induced and charge is conducted through the oxides. Thick oxides generally behave in a manner that is typical of insulators, that is they will tolerate an increasing field until a certain high potential, then the oxide will break down. Below this breakdown, there is only a small current (called Fowler-Nordheim tunneling). Then, at a certain voltage level, the current will rise sharply, and significant charge will flow through the oxide. If the current is large enough, damage will occur to the oxide, and the oxide will become conductive. In some cases, one breakdown event may not be enough to cause the oxide to change permanently to a conductive state. Rather, a series of breakdown events are needed to cause the oxide to become conductive. In thinner oxides, there can be other modes of conduction, such as direct tunneling, and these currents may prevent the easy build up of voltage across the oxide. As the voltage increases, the current through the oxide will increase, and likewise the current will decrease if the voltage is decreased. These oxides must typically conduct a significant amount of charge before the insulating characteristics are lost. This charge to breakdown amount (Q_(bd)) must be driven through the insulator to cause it to change states, from an insulator to a conductor.

[0025] In particular, in the embodiment of FIG. 2, the transistor M1 is the dielectric breakdown device or antifuse element. In one example, NODES 5 and 6 are held near zero volts or ground, and NODE 4 is driven to a high voltage for writing to the antifuse device M1. To drive NODE 4 to a high voltage level, a pre-charge step may be used in conjunction with a voltage boost step. In the pre-charge step, transistor M2 is used to charge up the programming NODE 4 to a first pre-charge voltage level. To effect this pre-charge step, a voltage, such as a voltage near the supply voltage (Vdd) or preferably a pumped supply voltage (Vpp), is applied to NODE 2 of the access transistor M2, and a voltage at least a Vth above the Vpp level is applied to NODE 1 (Vpp+Vth, where Vth is the threshold voltage of M2). This pre-charge step will drive NODE 4 to Vpp level. In the voltage boost operation, NODE 4 is first isolated by reducing the voltage at NODE 1 to a Vpp level or below thereby turning “off” the access transistor M2. To boost the voltage at NODE 4 to the high voltage needed for writing or breaking down the dielectric of the antifuse element M1, a Vpp level voltage pulse is applied to NODE 3 of capacitor C1. Due to the nature of capacitors, this action causes NODE 4 to rise along with NODE 3, thereby raising NODE 4 to a high level voltage, for example, of approximately 2-times Vpp or 2Vpp, assuming NODE 4 was precharged to a Vpp voltage level. Thus, this circuit configuration allows for raising the internal programming voltage within the non-volatile memory cell to a higher voltage, such as a voltage that is two-times or more than the voltages being applied to the capacitor C1 and the access transistor M2.

[0026] In this write operation, therefore, the disclosed memory cell structure of FIG. 2 can double the applied voltage inside the memory element or cell 200. This capability of doubling the applied voltage in the cell is a significant benefit of the disclosed structure. This feature, therefore, allows the memory cell to be made without high voltage transistors throughout the design by confining the high voltage to a single node in the memory cell. This doubling within the cell allows the other circuitry that drives the memory core to operate at lower voltages, for example, at Vcc or Vpp. Special high voltage transistors are not required to deliver to the memory core the high voltages that are needed to write the memory elements. In the structure of FIG. 2, the high voltage appears across the dielectric of antifuse element M1 and is confined to NODE 4. In the example above, therefore, the voltage across the access transistor M2 and capacitor C1 is Vpp, and the voltage across the dielectric of the antifuse element M1 is 2Vpp. It is noted that the FIG. 2 depicts the use of an antifuse element M1 that is capable of being written to once because the dielectric breakdown is typically not reversible once it has occurred. However, the internal memory cell voltage doubling technique could also be used with other memory elements that could be re-writable, if desired. It is further noted that the voltage boosting technique of the present invention could be utilized to drive the internal programming voltages of the non-volatile memory cell to an even higher voltages that exceed a voltage that is double the voltage being applied to the capacitor or to the access devices for the non-volatile memory cell, if such higher voltages were desired for a particular implementation. In addition, the voltage boosting technique could also be used to generate internal programming voltages that are higher then the applied voltages but lower than double the applied voltages. In short, a wide range of elevated voltages could be achieved, as desired, utilizing the capacitor voltage boosting technique of the present invention.

[0027] To read the state of the antifuse element M1, a voltage is applied across the antifuse element and then read circuitry will detect if there is a current flow through the dielectric of the antifuse element. For example, NODE 2 can be driven to an initial voltage, such as 1 volt, and NODE 1 can be driven to a positive voltage, such as Vdd. If the dielectric within the antifuse element M1 is conducting, a current will flow from NODE 2, through transistor M2 to NODE 4 and then to NODE 5 and/or NODE 6 through the dielectric of antifuse M1. If the dielectric within the antifuse element M1 is not conducting, then there would be no current flowing from NODE 2 to the antifuse element M1. The current flow determination and the no current flow determination are then used to determine the resistivity state of the antifuse element and thereby to determine the logic state of the non-volatile memory cell 200. For example, dielectric breakdown and associated current flow could define a logic “1,” and no dielectric breakdown and no current flow could define a logic “0.”

[0028] As indicated above with respect to FIGS. 1A and 1B, the memory cell structure 200 of FIG. 2 can be used in an array of write-once memory cells, and the read selection of an individual cell can be done by the respective voltages applied to the NODE 1 and NODE 2 of the individual cells. For example, NODE 1 could be used to select a row of non-volatile memory cells in an array, while the column could be selected through NODE 2. This implementation is further discussed with respect to FIG. 5B below.

[0029] Advantageously, therefore, the benefits of the non-volatile embedded memory cell structure of the present invention include: (1) a programming voltage generated internally to the memory cell, (2) no high voltage transistors needed for routing the high programming voltage to the memory cell, (3) unique selection of the memory cell is possible through the use of NODE 1 and NODE 2, and/or (4) no special structures, special processing techniques and/or process modifications are required to integrate the non-volatile memory cell structure with other CMOS circuitry.

[0030]FIG. 3A is a cross-section diagram for the non-volatile antifuse element (M1) 206. In this embodiment, for the antifuse element 206 is fabricated as an NMOS transistor device. For example, the substrate 310 can be p-type with an n-type channel existing between the source 306 and the drain 308, which are both n-type. The gate 302 sits above the channel region and sits on top of a dielectric layer 304. With respect to FIG. 2, NODE 4 is connected to the gate 302, NODE 5 is connected to the source 306, and NODE 6 is connected to the drain 308. In addition, as depicted in FIG. 3A, the source 306 and the drain 308 are both coupled to a ground voltage level. It is noted that other device types could be utilized for the antifuse element, such as PMOS transistor devices, devices that have a dielectric layer positioned between two conductive layers, and/or any other device element that is configured to have reduced resistivity after a programming node is subjected to one or more voltage pulses such that a change in resistivity can represent a change in logic state.

[0031] The dielectric 304, usually silicon dioxide, requires that a certain amount of current pass through an area of the oxide to cause it to become conductive. In thicker dielectrics, this breakdown can happen rather quickly when a large voltage is applied. Thus, a very high but very short pulse of current will often cause conduction and will generally cause conduction in the weakest part or parts of the dielectric, such as defect or charge trap locations. If there are several weak spots in the oxide, then current will often be shared through these weak areas. In thinner dielectrics, however, the oxide will conduct current more uniformly across the area of the dielectric. As a voltage is applied, the oxide will conduct and load down the applied voltage, thereby tending to decrease the voltage across the oxide. In most cases, the available current is limited. As such, it is desirable to minimize the oxide area that is conducting and to concentrate the current in as small of an area as possible. This concentration will reduce the total amount of current that is needed to conduct through the oxide to cause breakdown and/or will reduce the time that is needed to achieve breakdown of the oxide.

[0032] With respect to FIG. 3A and dielectric 304, therefore, it is desirable to fabricate the antifuse element 206 with a minimal area for the dielectric 304. For example, the area of the dielectric 304 may be fabricated using minimum dimensions for the gate oxide area that are allowed with respect to the integrated circuit being fabricated. These minimum dimensions are typically provided by the manufacturer, and no structure can typically be used in the layout of the memory element that is smaller than the dimensions allowed by the manufacturing processes being utilized.

[0033]FIG. 3B depicts a technique that can be used to further reduce the effective area of the dielectric for the memory element by generating a lateral electric field to concentrate the current flow through the dielectric. FIG. 3B is a cross-section diagram for an alternative embodiment for the non-volatile antifuse element M1 in which a voltage gradient is utilized. The enhancement added to FIG. 3B over FIG. 3A is the application of a higher voltage, such as 2 volts, to the drain 308 as compared to the voltage applied to the source 306, such as ground. The voltage difference between the drain 308 and the source 306 creates a voltage gradient 312 across the channel region of the transistor M1.

[0034] The voltage gradient across the channel causes the voltage from the gate to the channel to vary from one end of the channel to the other. The end of the channel that has the higher voltage applied will have less vertical field across the oxide than the end of the channel with the lower voltage applied. Because the current through the oxide is dependent on the voltage across the oxide, the area of the gate where the highest voltage difference appears tends to be the area that conducts the most current. If the gate voltage is uniform across its entire area, the voltage across the oxide will then depend on the voltage of the channel region below the gate. For example, where 2 volts and ground are used as different voltage levels to create a voltage gradient, the end of the channel with 2 volts applied will have about Vgate-2 volts applied across the dielectric, where as the end of the channel at ground will have the full Vgate applied voltage applied across the dielectric. This voltage gradient will cause the current to crowd into the area where the highest field is applied and thereby reduce the current in the rest of the channel.

[0035] In thick oxides, the concentration of current near the source will likely cause the dielectric to breakdown quickly because fewer weak spots in the dielectric have the highest electric field applied to them. This concentration will reduce the time and current needed to break down the thicker dielectric and will cause the breakdown to be near the source. With the breakdown near the source, the resistance of the final programmed memory element will also be reduced because the electric path will be from the source to a path in the oxide near the source. If the voltage gradient is not present in the channel of the transistor, the breakdown can occur anywhere in the channel. If the breakdown is in the center of the channel, for example, then the current path will be longer and result in a higher total resistance.

[0036] In thin oxides, the amount of current (or charge called Q_(bd)—charge to breakdown) needed to break down the oxide is relatively large because the oxide is typically uniform and will conduct current throughout the entire area of the oxide. This current flow through the oxide slowly causes a degradation. Because there is usually a limited amount of current available, it is desirable to concentrate this current into the smallest area possible. The voltage gradient across the channel, such as that depicted in FIG. 3B, will tend to cause the highest electrical field to appear in the region of the channel near the source. And the field will decrease as the distance from the source increases, causing less current to flow in those areas. This voltage gradient, therefore, will effectively concentrate the current in the area near the source and reduce the total amount of current needed to breakdown the structure.

[0037] FIGS. 4A-4B are a cross-section perspective diagrams for further embodiments for the non-volatile antifuse element M1 in which additional voltage gradients are utilized. These embodiments further guide or crowd the current by applying a lateral field perpendicular to or in addition to the gradient that is formed across the channel. This additional lateral field can be created, for example, using a voltage gradient formed within the gate region and/or formed on one side of the channel using the source or drain regions.

[0038]FIG. 4A provides an example embodiment where an additional voltage gradient has been formed in the gate region. Compared to FIG. 3B, the embodiment in FIG. 4A adds one voltage 405, such as Vg, applied to one end of the gate region and a second lower voltage 403, such as Vg-2, applied to the other end of the gate region. These voltages create an additional lateral voltage gradient that is roughly perpendicular to the voltage gradient 312 generated in the channel. This additional voltage gradient tends to guide or urge breakdown to occur near POINT A 401, which represents a region that is close to the source 306 and close to the front of the antifuse element 206 as depicted in FIG. 4A. The highest electric field across the oxide appears in the immediate area of POINT A, where the channel voltage is 0 volts, and where the rest of the channel has a voltage above 0 volts, the voltage gradients will cause breakdown to occur at or near POINT A.

[0039]FIG. 4B provides another example embodiment where an additional voltage gradient has been formed in the source region. Compared to FIG. 3B, the embodiment in FIG. 4B adds one voltage 406, such as 2 volts, applied to one end of the source region and a second lower voltage 408, such as ground, applied to the other end of the source region. The drain region includes two ends as well, and as depicted, these ends are both kept at the higher voltage, such as 2 volts, as represented by voltages 402 and 404. The voltage differences in the source region create an additional lateral voltage gradient that is roughly perpendicular to the voltage gradient 312 generated in the channel. This additional voltage gradient tends to urge breakdown to occur near POINT B 407, which represents a region that is close to the source 306 and close to the front of the antifuse element 206 as depicted in FIG. 4B, again where the highest electric field is present across the oxide.

[0040] The benefits of using one or more voltage gradients within the antifuse element 206, therefore, include: (1) a reduction in the effective area of the dielectric that is conducting current, (2) guiding and confining the highest electric field to the area close to the source or drain connection, (3) making more consistent the resistance of the conductive oxide by causing the breakdown to occur consistently near the source, and (4) focusing the oxide breakdown to occur near a particular region or point within the dielectric. It is noted that the use of one or more voltage gradients could be implemented and configured in a variety of ways, as desired, to achieve the advantages provided by the use of voltage gradients. FIG. 3B simply provides one example of how a single voltage gradient could be utilized to focus current flow and oxide breakdown. And FIGS. 4A and 4B simply provide examples of how multiple gradients could be utilized to focus current flow and oxide breakdown.

[0041] The above described structures produce antifuse elements that can be programmed with internally generated high voltage. Preferably, a single pulse could be used to cause breakdown and write the antifuse element. However, it may often be the case that a single pulse of sufficient voltage may not be practical and that available on-chip voltages for a single pulse may be insufficient to breakdown the structure. In such cases, therefore, a programming method can be utilized, such as a series of voltage pulses, to make sure that the element is programmed by quickly reaching the required Q_(bd) to cause breakdown of the dielectric.

[0042] As discussed above with respect to FIG. 2, the breakdown charge is supplied by the capacitor C1, and this charge is limited by the amount of charge stored by the capacitor. In other words, the current through the oxide is dependent on the applied voltage, and to increase the current through the oxide, a maximum voltage is desirably applied. The structure of FIG. 2 relies upon the charge stored in the capacitor C1, and as the current flows through the dielectric, the voltage on the capacitor C1 decreases. This decrease in voltage will cause a significant decrease in current flow. Capacitor C1 is first pre-charged to a voltage level through transistor M2, while NODE 3 is held to ground, then NODE 3 is boosted to produce a large voltage on NODE 4. Therefore, to quickly attain the Q_(bd) through the dielectric, the capacitor C1 can be recharged shortly after it is boosted, so that the voltage can be restored and again applied to the dielectric. This repetitive charging and boosting to apply high voltage peaks to the dielectric will tend to maximize the current flow through the oxide and allow the element to be programmed in a short time period.

[0043] Thus, to better utilize the above described structure for a programmable memory element, it is desirable to utilize a programming method that rapidly and repeatedly pulses the memory element with high voltages pulses. This pulsing will then produce the required current through the oxide to cause the degradation and subsequent breakdown that is required to program or write the antifuse element. The actual implementation can be done in many ways. Two basic approaches to writing the antifuse element with this multiple pulse technique include: (1) using a fixed number of pulses that can be applied rapidly and then sensing the state of the cell to see if the write is complete, and (2) using pulses and continuously monitoring the state of the cell to detect if the write has completed. The second technique, however, has the drawback that the frequency of the pulses may be limited to allow time for the state of the element to be correctly detected.

[0044]FIG. 5A is a graphical diagram for writing to the non-volatile antifuse element M1 including voltage pulses at NODE 4 of FIG. 2 and corresponding current flows through NODE 4. In particular, graph 500 represents voltage pulses applied to NODE 4, and graph 510 represents corresponding current flow through NODE 4 into the antifuse element M1. As discussed above, NODE 4 is first pre-charged to a voltage, such as Vpp. Then, the capacitor C1 is hit with a voltage pulse of Vpp, thereby driving NODE 4 to approximately 2Vpp. Each spike 502A, 502B, 502C . . . represents one of these pulsing events, and each current spike 506A, 506B, 506C . . . represents a corresponding rapid current flow into the antifuse element M1. If desired, the pre-charging event can also occur each cycle so that NODE 4 is brought back to Vpp before the next pulse. Each voltage drop 504A, 504B, 504C . . . represents one of these pre-charging events. As depicted in FIG. 5A, each pulse is separated from the previous pulse by a finite time amount 512. It is noted that the number of pulses and the time between pulses can be modified, as desired. The pulses can be, for example, about 1000 pulses or more spaced at 30-50 nanoseconds apart or less. This pulse cycle can then be followed by a read cycle where it is verified whether or not the write was effective.

[0045] The rapid pulse cycle technique provides a number of advantages, including: (1) sufficient current can be supplied by rapid pulses, (2) a small capacitor can be exchanged for large number of pulses of current within the antifuse element 206, and (3) high frequency operation can result in relatively fast program times.

[0046]FIG. 5B is an example block diagram depicting non-volatile memory cells according to the present invention coupled to write control circuitry 554 including a pulse generator 556 and coupled to pre-charge and read control circuitry 552. The memory array architecture 550 includes a plurality of non-volatile memory cells, which include antifuse elements 206A, 206B, 206C . . . , access devices 202A, 202B, 202C . . . , and boost capacitors 204A, 204B, 204C . . . , respectively. The source nodes (NODE 5) of the antifuse elements are coupled to line 558, and the drain nodes (NODE 6) of the antifuse elements are coupled to line 560. As discussed above, lines 558 and 560 can be used to generate a voltage gradients within the antifuse elements.

[0047] Row select circuitry 551 can be coupled to the control nodes (NODE 1) for access devices 202A, 202B, 202C . . . to provide access control to the internal programming nodes (NODE 4) and the antifuse elements 206A of the non-volatile memory cells. The row select circuitry 551 can also provide the row selection within an array of non-volatile memory cells. Column select, read and pre-charge circuitry 552 can be coupled to output nodes (NODE 2) of the non-volatile memory cells to provide read and pre-charge operations, as discussed above. The circuitry 552 can also provide the column selection within an array of non-volatile memory cells. Write control circuitry 554, including a pulse generator 556, can be coupled to the input nodes (NODE 3) of the boost capacitors 204A, 204B and 204C to provide the voltage boost and pulse cycle activities discussed with respect to FIG. 5A above. Using the pulse write cycle implementation discussed above, the read portion of circuitry 552 can also be used to provide the verification operation to determine if the pulse cycle had been effective in writing to the antifuse elements. It is noted that a wide variety of implementations could be utilized, as desired, with respect to the organization of the non-volatile memory cells of the present invention. Thus, the particular organization provided in FIG. 5B should be understood as just one example for how the row and column circuitry could be organized. One such modified organization, for example, could be to swap the row and column designations as they are depicted in FIG. 5B, such that NODE 2 of each non-volatile memory cell is used for row selection, and NODE 1 of each non-volatile memory cell is used for column selection.

[0048] Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the present invention is not limited by these example arrangements. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as the presently preferred embodiments. Various changes may be made in the implementations and architectures for database processing. For example, equivalent elements may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. 

What is claimed is:
 1. A method for utilizing a plurality of voltage pulses to program a non-volatile memory cell integratable with other CMOS circuitry, comprising: providing an antifuse element having a programming node, the antifuse element being configured to have reduced resistivity after the programming node is subjected to a plurality voltage pulses, the change in resistivity representing a change in logic state, wherein the antifuse element comprises a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the plurality of voltage pulses; coupling a capacitor element to the programming node of the antifuse element, the capacitor element being configured to provide the plurality of voltage pulses to the programming node; and writing to the non-volatile memory cell by applying a plurality of voltage pulses to the capacitor element.
 2. The method of claim 1, further comprising coupling an access element to the programming node, the access element configured to allow determination of the logic state for the antifuse element.
 3. The method of claim 1, further comprising coupling an access element to the programming node, and wherein the writing step comprises, for each applied voltage pulse, pre-charging the programming node to a first voltage through the access element and then applying a voltage pulse to the capacitor to thereby elevate the programming node to a boosted voltage, the boosted voltage acting to urge the change in resistivity of the antifuse element.
 4. The method of claim 3, wherein the boosted voltage exceeds double the first voltage.
 5. The method of claim 3, wherein the access element comprises a MOS transistor having its gate coupled to a control node and having its source and drain coupled between the programming node and an external node.
 6. The method of claim 3, further comprising verifying whether the antifuse element was successfully written by determining the logic state of the non-volatile memory cell by accessing the programming node through the access element, the current flowing through the programming node representing the logic state of that non-volatile memory cell and a successful writing event being indicated by a change in the resistivity of the antifuse element.
 7. The method of claim 6, further comprising repeating the writing step and the verifying step until the verifying step indicates that the antifuse element has been successfully written.
 8. The method of claim 1, wherein the plurality of voltage pulses comprise a plurality of voltage pulses with each pulse being some finite time amount of time apart from each successive pulse.
 9. The method of claim 8, wherein the number of pulses is greater than 1000 pulses and the finite time amount is 50 nanoseconds or less.
 10. The method of claim 1, further comprising checking the logic state of the non-volatile memory cell to verify whether or not the writing step was successful, and repeating the writing and checking steps until the writing step is determined to have been successful.
 11. The method of claim 1, further comprising generating one or more voltage gradients within the antifuse element in order to guide a location for breakdown to occur within the dielectric layer of the antifuse element.
 12. The method of claim 11, wherein the one or more voltage gradients are generated by coupling two or more different voltage levels to the source, the drain and the gate of the MOS transistor antifuse element.
 13. An embedded non-volatile memory integrated with other CMOS circuitry, comprising: a plurality of non-volatile memory cells, each cell comprising: an antifuse element having a programming node, the antifuse element being configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses, the change in resistivity representing a change in logic state, wherein the antifuse element comprises a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the plurality of voltage pulses; a capacitor element coupled to the antifuse element and configured to provide a plurality of voltage pulses to the programming node; and an access element coupled to the programming node, the access element configured to allow determination of the logic state for the antifuse element; and write circuitry coupled to the capacitor elements of the plurality of non-volatile memory cells, the write circuitry configured to generate the plurality of voltage pulses and to provide them to the capacitor elements.
 14. The embedded non-volatile memory of claim 13, further comprising read circuitry coupled to access the programming nodes of the plurality of non-volatile memory cells through the access elements and to determine a logic state of one or more non-volatile memory cells, the current flowing through each programming node representing the logic state of that non-volatile memory cell.
 15. The embedded non-volatile memory of claim 13, wherein a plurality of the non-volatile memory cells are written simultaneously.
 16. The embedded non-volatile memory of claim 13, further comprising write verification circuitry coupled to access the programming nodes of the plurality of non-volatile memory cells through the access elements and to determine a logic state of a written memory cell in order to verify a successful write operation, the current flowing through each programming node representing the logic state of that non-volatile memory cell.
 17. The embedded non-volatile memory of claim 13, wherein the plurality of voltage pulses are configured such that each voltage pulse spaced apart from a successive voltage pulse by a finite amount of time.
 18. The embedded non-volatile memory of claim 17, wherein the wherein the number of pulses is greater than 1000 pulses and the finite time amount is 50 nanoseconds or less.
 19. The embedded non-volatile memory of claim 13, wherein the write circuitry is further configured, for each applied voltage pulse, to pre-charge the programming node to a first voltage through the access element and then to apply a voltage pulse to the capacitor to thereby elevate the programming node to a boosted voltage, the boosted voltage acting to urge the change in resistivity of the antifuse element.
 20. The embedded non-volatile memory of claim 19, wherein the boosted voltage exceeds double the first voltage.
 22. The embedded non-volatile memory of claim 13, further comprising two or more voltage levels coupled to each antifuse element to generate one or more voltage gradients, the voltage gradients guiding a location for breakdown to occur within the dielectric layer.
 23. The embedded non-volatile memory of claim 22, wherein the one or more voltage gradients for each antifuse element are generated by coupling two or more different voltage levels to the sources, the drains and the gates of the MOS transistor antifuse elements.
 24. The embedded non-volatile memory of claim 13, further comprising row selection circuitry and column selection circuitry coupled to each of the antifuse elements. 